70 search results - page 3 / 14 » Efficient Fault Tolerance: An Approach to Deal with Transien... |
RTS
2006
13 years 7 months ago
2006
Abstract. The Time-Triggered Architecture, as architecture for safety-critical realtime applications, incorporates fault-tolerance mechanisms to ensure correct system operation des...
EDCC
2008
Springer
13 years 9 months ago
2008
Springer
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
FPGA
2003
ACM
14 years 20 days ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
CAL
2006
13 years 7 months ago
2006
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...
HICSS
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents how state consistency among distributed control nodes is maintained in the presence of faults. We analyze a fault tolerant semi-synchronous architecture concep...