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» Efficient Hardware Architecture for Fast IP Address Lookup
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ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
14 years 12 hour ago
Fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
HPCA
2007
IEEE
14 years 8 months ago
HARD: Hardware-Assisted Lockset-based Race Detection
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
Pin Zhou, Radu Teodorescu, Yuanyuan Zhou
ASPDAC
2008
ACM
108views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block sel
Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due t...
Jui-Yuan Hsieh, Shanq-Jang Ruan
SIGMOD
2007
ACM
164views Database» more  SIGMOD 2007»
14 years 7 months ago
Fast data stream algorithms using associative memories
The primary goal of data stream research is to develop space and time efficient solutions for answering continuous online summarization queries. Research efforts over the last dec...
Nagender Bandi, Ahmed Metwally, Divyakant Agrawal,...
ASAP
2000
IEEE
90views Hardware» more  ASAP 2000»
14 years 4 days ago
Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures
MicroSIMD architectures incorporating subword parallelism are very efficient for application-specific media processors as well as for fast multimedia information processing in gen...
Ruby B. Lee