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» Efficient Hardware Controller Synthesis for Synchronous Data...
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SAC
2010
ACM
13 years 9 months ago
Reactive parallel processing for synchronous dataflow
The control flow of common processors does not match the specific needs of reactive systems. Key issues for these systems are preemption and concurrency, combined with timing pred...
Claus Traulsen, Reinhard von Hanxleden
DATE
1999
IEEE
139views Hardware» more  DATE 1999»
13 years 11 months ago
OpenJ: An Extensible System Level Design Language
There is an increasing research interest in system level design languages which can carry designers from specification to implementation of system-on-a-chip. Unfortunately, two of...
Jianwen Zhu, Daniel Gajski
DATE
2002
IEEE
105views Hardware» more  DATE 2002»
14 years 13 days ago
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
Chunhong Chen, Majid Sarrafzadeh
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
13 years 11 months ago
Efficient High-Level modeling in the networking domain
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...
Christian Zebelein, Joachim Falk, Christian Haubel...
AOSD
2008
ACM
13 years 9 months ago
AJANA: a general framework for source-code-level interprocedural dataflow analysis of AspectJ software
Aspect-oriented software presents new challenges for the designers of static analyses. Our work aims to establish systematic foundations for dataflow analysis of AspectJ software....
Guoqing Xu, Atanas Rountev