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AHS
2006
IEEE
195views Hardware» more  AHS 2006»
14 years 1 months ago
An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter
This paper presents an efficient hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264 video coding standard. This hardware is d...
Mustafa Parlak, Ilker Hamzaoglu
DATE
2006
IEEE
74views Hardware» more  DATE 2006»
14 years 1 months ago
Hardware efficient architectures for Eigenvalue computation
Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Ch...
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
14 years 1 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
FCCM
2005
IEEE
89views VLSI» more  FCCM 2005»
14 years 29 days ago
A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms
Although researchers have presented individual techniques to efficiently utilize the Peripheral Component Interconnect (PCI) bus, their contributions fail to provide a direct path...
Petersen F. Curt, James P. Durbano, Fernando E. Or...
IPPS
2008
IEEE
14 years 1 months ago
Energy efficient packet classification hardware accelerator
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
Alan Kennedy, Xiaojun Wang, Bin Liu