279 search results - page 14 / 56 » Efficient Power Co-Estimation Techniques for System-on-Chip ... |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—This paper describes a new low-power, area and pin efficient alternative to differential encoding for high performance chip-to-chip and backplane signaling. The technique, calle...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
CHI
2007
ACM
14 years 7 months ago
2007
ACM
On traditional tables, people frequently use the third dimension to pile, sort and store objects. However, while effective and informative for organization, this use of the third ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...