279 search results - page 15 / 56 » Efficient Power Co-Estimation Techniques for System-on-Chip ... |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
IJCAI
2003
13 years 8 months ago
2003
Efficient implementations of DPLL with the addition of clause learning are the fastest complete satisfiability solvers and can handle many significant real-world problems, such as...
ASAP
2009
IEEE
13 years 10 months ago
2009
IEEE
An implementation of a radix-4 approximate squaring circuit is described employing a new operand dual recoding technique. Approximate squaring circuits have numerous applications ...
PPL
2008
13 years 7 months ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
SOFSEM
2000
Springer
13 years 11 months ago
2000
Springer
For half a century since computers came into existence, the goal of finding elegant and efficient algorithms to solve "simple" (welldefined and well-structured) problems ...