279 search results - page 34 / 56 » Efficient Power Co-Estimation Techniques for System-on-Chip ... |
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
A new high performance computation technique involving multiple processors on a single silicon die is quickly gaining popularity. This new design approach provides very high perfo...
ISCA
2010
IEEE
14 years 24 days ago
2010
IEEE
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
Energy efficiency is a primary concern for microprocessor designers. A very effective approach to improving the energy efficiency of a chip is to lower its supply voltage to very ...
VLSID
2009
IEEE
14 years 9 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
ICCD
2001
IEEE
14 years 5 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...