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CAV
2006
Springer
132views Hardware» more  CAV 2006»
13 years 11 months ago
Symmetry Reduction for Probabilistic Model Checking
We present an approach for applying symmetry reduction techniques to probabilistic model checking, a formal verification method for the quantitative analysis of systems with stocha...
Marta Z. Kwiatkowska, Gethin Norman, David Parker
COMPSAC
2003
IEEE
14 years 20 days ago
A Cut-Based Algorithm for Reliability Analysis of Terminal-Pair Network Using OBDD
In this paper, we propose an algorithm to construct the Ordered Binary Decision Diagram (OBDD) representing the cut function of a terminal-pair network. The algorithm recognizes i...
Yung-Ruei Chang, Hung-Yau Lin, Ing-Yi Chen, Sy-Yen...
DATE
1998
IEEE
103views Hardware» more  DATE 1998»
13 years 11 months ago
Efficient Encoding Schemes for Symbolic Analysis of Petri Nets
Petri nets are a graph-based formalism appropriate to model concurrentsystems such as asynchronouscircuits or network protocols. Symbolic techniques based on Binary Decision Diagr...
Enric Pastor, Jordi Cortadella
ICCAD
1996
IEEE
93views Hardware» more  ICCAD 1996»
13 years 11 months ago
VERILAT: verification using logic augmentation and transformations
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatter...
ASPDAC
1998
ACM
72views Hardware» more  ASPDAC 1998»
13 years 11 months ago
Space- and Time-Efficient BDD Construction via Working Set Control
Binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. Efficient BDD construction techniques become more important as the complexity of proto...
Bwolen Yang, Yirng-An Chen, Randal E. Bryant, Davi...