14 search results - page 3 / 3 » Efficient Scan Chain Design for Power Minimization During Sc... |
DAC
2007
ACM
14 years 7 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...
DAC
2005
ACM
13 years 8 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...