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VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
16 years 4 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
DAC
2006
ACM
15 years 10 months ago
Use of C/C++ models for architecture exploration and verification of DSPs
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
David Brier, Raj S. Mitra
WSC
2004
15 years 5 months ago
Comparative Factory Analysis of Standard FOUP Capacities
Wafers in a 300-mm semiconductor fabrication facility are transported throughout the factory in carriers called front opening unified pods (FOUPs). Two standard capacities of FOUP...
Kranthi Mitra Adusumilli, Robert L. Wright
IISWC
2008
IEEE
15 years 11 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
WSC
2007
15 years 6 months ago
Hierarchical planning and multi-level scheduling for simulation-based probabilistic risk assessment
Simulation of dynamic complex systems—specifically, those comprised of large numbers of components with stochastic behaviors—for the purpose of probabilistic risk assessment f...
Hamed Nejad, Dongfeng Zhu, Ali Mosleh