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ISQED
2002
IEEE
14 years 9 days ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
FPL
2010
Springer
13 years 5 months ago
2010
Springer
Abstract--Modular multiplication of long integers is an important building block for cryptographic algorithms. Although several FPGA accelerators have been proposed for large modul...
SIGOPS
2010
13 years 2 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
CASES
2003
ACM
14 years 19 days ago
2003
ACM
Knowing the Worst-Case Execution Time (WCET) of a program is necessary when designing and verifying real-time systems. A correct WCET analysis method must take into account the po...
IEEEINTERACT
2003
IEEE
14 years 20 days ago
2003
IEEE
This paper introduces a method for improving program run-time performance by gathering work in an application and executing it efficiently in an integrated thread. Our methods ext...