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» Efficient Software-Based Fault Isolation
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CSREAESA
2008
13 years 9 months ago
BIST-BASED Group Testing for Diagnosis of Embedded FPGA Cores
A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by ex...
Alireza Sarvi, Carthik A. Sharma, Ronald F. DeMara
ICPADS
1998
IEEE
13 years 11 months ago
The XBW Model for Dependable Real-Time Systems
This paper presents a new conceptual model, the XBWModel. Distributed computing is becoming a cost effective way to implement safety critical control systems. To support the devel...
Vilgot Claesson, Stefan Poledna, Jan Söderber...
DAC
2007
ACM
14 years 8 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2003
ACM
14 years 8 months ago
A survey of techniques for energy efficient on-chip communication
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...
IPSN
2007
Springer
14 years 1 months ago
Harbor: software-based memory protection for sensor nodes
Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no...
Ram Kumar, Eddie Kohler, Mani B. Srivastava