In this paper, we first present a concrete formal protocol design approach, which is based on authentication tests, to create an Efficient and Secure Internet Key Exchange (ESIKE)...
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
Pseudo-exhaustive testing uses the empirical observation that, for broad classes of software, a fault is likely triggered by only a few variables interacting. The method takes adv...
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valent...
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...