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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
14 years 11 days ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
SPIN
2010
Springer
13 years 5 months ago
Efficient Explicit-State Model Checking on General Purpose Graphics Processors
We accelerate state space exploration for explicit-state model checking by executing complex operations on the graphics processing unit (GPU). In contrast to existing approaches en...
Stefan Edelkamp, Damian Sulewski
SARA
2000
Springer
13 years 11 months ago
Improving the Efficiency of Reasoning Through Structure-Based Reformulation
We investigate the possibility of improving the efficiency of reasoning through structure-based partitioning of logical theories, combined with partitionbased logical reasoning str...
Eyal Amir, Sheila A. McIlraith
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
14 years 8 months ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
14 years 8 months ago
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing
In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as t...
Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun...