The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved perfo...
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
The computation of covariance and correlation matrices are critical to many data mining applications and processes. Unfortunately the classical covariance and correlation matrices...
James Chilson, Raymond T. Ng, Alan Wagner, Ruben H...
We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulatio...
Originally, the hierarchical coding structure was proposed to achieve temporal scalability. Soon after, it was realized that with a proper quantization parameter cascading (QPC) s...