544 search results - page 102 / 109 » Efficient checker processor design |
TVLSI
2008
13 years 9 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
SIGGRAPH
2000
ACM
14 years 2 months ago
2000
ACM
We present the WarpEngine, an architecture designed for realtime image-based rendering of natural scenes from arbitrary viewpoints. The modeling primitives are real-world images w...
PPOPP
2009
ACM
14 years 10 months ago
2009
ACM
GPGPUs have recently emerged as powerful vehicles for generalpurpose high-performance computing. Although a new Compute Unified Device Architecture (CUDA) programming model from N...
HPCA
2008
IEEE
14 years 10 months ago
2008
IEEE
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
ITC
2003
IEEE
14 years 3 months ago
2003
IEEE
As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk...