555 search results - page 16 / 111 » Efficient event-driven simulation of parallel processor arch... |
98
Voted
SPAA
1992
ACM
15 years 6 months ago
1992
ACM
A global barrier synchronizes all processors in a parallel system. This paper investigates algorithms that allow disjoint subsets of processors to synchronize independently and in...
140
Voted
ARCS
2008
Springer
15 years 4 months ago
2008
Springer
: Sorting large data sets has always been an important application, and hence has been one of the benchmark applications on new parallel architectures. We present a parallel sortin...
139
Voted
MICRO
2010
IEEE
15 years 21 days ago
2010
IEEE
Wide Single Instruction, Multiple Thread (SIMT) architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application ker...
137
Voted
TCAD
2002
15 years 2 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
126
Voted
VRIPHYS
2010
14 years 9 months ago
2010
In this paper, we present a set of methods to improve numerical solvers, as used in real-time non-linear deformable models based on implicit integration schemes. The proposed appr...