555 search results - page 92 / 111 » Efficient event-driven simulation of parallel processor arch... |
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved ...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
HPDC
2009
IEEE
14 years 2 months ago
2009
IEEE
Since the advent of electronic computing, the processors’ clock speed has risen tremendously. Now that energy efficiency requirements have stopped that trend, the number of proc...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
Multi-core processors have changed the conventional hardware structure and require a rethinking of system scheduling and resource management to utilize them efficiently. However, ...