555 search results - page 9 / 111 » Efficient event-driven simulation of parallel processor arch... |
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
MASCOTS
2007
13 years 9 months ago
2007
—Modern micro-architecture simulators are many orders of magnitude slower than the hardware they simulate. The use of multiprocessor architectures for supporting future mobile an...
ISCAPDCS
2003
13 years 9 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
PARELEC
2000
IEEE
13 years 12 months ago
2000
IEEE
The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on X...
ICPP
2008
IEEE
14 years 2 months ago
2008
IEEE
The shading processors in graphics hardware are becoming increasingly general-purpose. We test, through simulation and benchmarking, the potential performance impact of replacing ...