101 search results - page 19 / 21 » Efficient utilization of scratch-pad memory in embedded proc... |
ANCS
2007
ACM
13 years 11 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
ECRTS
2005
IEEE
14 years 1 months ago
2005
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
LCTRTS
2005
Springer
14 years 29 days ago
2005
Springer
Real-time garbage collection has been shown to be feasible, but for programs with high allocation rates, the utilization achievable is not sufficient for some systems. Since a hi...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...