166 search results - page 14 / 34 » Efficient worst case timing analysis of data caching |
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transf...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
STOC
2006
ACM
14 years 1 months ago
2006
ACM
Memory management is a fundamental problem in computer architecture and operating systems. We consider a two-level memory system with fast, but small cache and slow, but large mai...
CODES
2001
IEEE
13 years 11 months ago
2001
IEEE
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may e...