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» Efficiently Implementing Episodic Memory
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PPOPP
2006
ACM
14 years 2 months ago
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hu...
ICS
2009
Tsinghua U.
14 years 1 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
MICRO
1997
IEEE
110views Hardware» more  MICRO 1997»
14 years 29 days ago
The Design and Performance of a Conflict-Avoiding Cache
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected i...
Nigel P. Topham, Antonio González, Jos&eacu...
RSP
1999
IEEE
125views Control Systems» more  RSP 1999»
14 years 1 months ago
Extended Synchronous Dataflow for Efficient DSP System Prototyping
Though synchronous dataflow (SDF) graph has been a successful input specification language for digital signal processing (DSP) applications, lack of support for global states makes...
Chanik Park, JaeWoong Chung, Soonhoi Ha
RTCSA
2008
IEEE
14 years 3 months ago
Scheduler-Assisted Prefetching: Efficient Demand Paging for Embedded Systems
In an attempt to substitute NOR flash with NAND flash and provide more memory to applications, embedded systems have to use demand paging. However, demand paging drastically degra...
Stanislav A. Belogolov, Jiyong Park, Jungkeun Park...