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» Efficiently generating test vectors with state pruning
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MTV
2007
IEEE
118views Hardware» more  MTV 2007»
14 years 1 months ago
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
Wang-Dauh Tseng, Lung-Jen Lee
DAC
2006
ACM
14 years 8 months ago
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty
The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail...
Ashish Kumar Singh, Murari Mani, Ruchir Puri, Mich...
ICES
2000
Springer
140views Hardware» more  ICES 2000»
13 years 11 months ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
ICST
2009
IEEE
14 years 2 months ago
PKorat: Parallel Generation of Structurally Complex Test Inputs
Constraint solving lies at the heart of several specification-based approaches to automated testing. Korat is a previously developed algorithm for solving constraints in Java pro...
Junaid Haroon Siddiqui, Sarfraz Khurshid
EH
2000
IEEE
123views Hardware» more  EH 2000»
13 years 12 months ago
The Test Vector Problem and Limitations to Evolving Digital Circuits
How do we know the correctness of an evolved circuit? While Evolutionary Hardware is exhibiting its effectiveness, we argue that it is very difficult to design a large-scale digit...
Kosuke Imamura, James A. Foster, Axel W. Krings