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DAC
2009
ACM
14 years 10 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
14 years 3 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 6 months ago
From molecular interactions to gates: a systematic approach
The continuous minituarization of integrated circuits may reach atomic scales in a couple of decades. Some researchers have already built simple computation engines by manipulatin...
Josep Carmona, Jordi Cortadella, Yousuke Takada, F...
ISPD
2009
ACM
112views Hardware» more  ISPD 2009»
14 years 4 months ago
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs
The multiple-supply voltage (MSV) design style has been extensively applied to mitigate dynamic-power consumption. The MSV design paradigm, however, brings many crucial challenges...
Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang
CHES
2009
Springer
171views Cryptology» more  CHES 2009»
14 years 10 months ago
Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering
Abstract. The general trend in semiconductor industry to separate design from fabrication leads to potential threats from untrusted integrated circuit foundries. In particular, mal...
Christof Paar, Lang Lin, Markus Kasper, Tim Gü...