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DAC
2008
ACM
14 years 8 months ago
On reliable modular testing with vulnerable test access mechanisms
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...
Lin Huang, Feng Yuan, Qiang Xu
DAC
2006
ACM
14 years 8 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu
DAC
2006
ACM
14 years 8 months ago
Novel full-chip gridless routing considering double-via insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...
RULEML
2005
Springer
14 years 27 days ago
Extending the SweetDeal Approach for e-Procurement Using SweetRules and RuleML
We show the first detailed realistic e-business application scenario that uses and exploits capabilities of the SweetRules V2.1 toolset for e-contracting using the SweetDeal approa...
Sumit Bhansali, Benjamin N. Grosof
DAC
2007
ACM
14 years 8 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram