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    GLVLSI
    2005
    IEEE
    124views VLSI» more  GLVLSI 2005»
    A first look at the interplay of code reordering and configurable caches
    14 years 1 months ago
    A first look at the interplay of code reordering and configurable caches
    Download  www.cs.ucr.edu
    The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
    Ann Gordon-Ross, Frank Vahid, Nikil Dutt
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    ISCAS
    2005
    IEEE
    128views Hardware» more  ISCAS 2005»
    Development of an audio player as system-on-a-chip using an open source platform
    14 years 1 months ago
    Development of an audio player as system-on-a-chip using an open source platform
    Download  www.ra.informatik.uni-stuttgart.de
    — Open source software are becoming more widely-used, notably in the server and desktop applications. For embedded systems development, usage of open source software can also red...
    Pattara Kiatisevi, Luis Leonardo Azuara-Gomez, Rai...
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    MICRO
    2005
    IEEE
    130views Hardware» more  MICRO 2005»
    Exploiting Vector Parallelism in Software Pipelined Loops
    14 years 1 months ago
    Exploiting Vector Parallelism in Software Pipelined Loops
    Download  groups.csail.mit.edu
    An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
    Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
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    RTAS
    2005
    IEEE
    191views Embedded Systems» more  RTAS 2005»
    Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
    14 years 1 months ago
    Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
    Download  moss.csc.ncsu.edu
    While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
    Harini Ramaprasad, Frank Mueller
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    ANCS
    2005
    ACM
    90views Computer Networks» more  ANCS 2005»
    Resource mapping and scheduling for heterogeneous network processor systems
    14 years 1 months ago
    Resource mapping and scheduling for heterogeneous network processor systems
    Download  www.public.asu.edu
    Task to resource mapping problems are encountered during (i) hardware-software co-design and (ii) performance optimization of Network Processor systems. The goal of the first pro...
    Liang Yang, Tushar Gohad, Pavel Ghosh, Devesh Sinh...
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