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SCOPES
2007
Springer
14 years 4 months ago
Efficient event-driven simulation of parallel processor architectures
Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, ...
ICCAD
2001
IEEE
184views Hardware» more  ICCAD 2001»
14 years 7 months ago
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
Cagdas Akturan, Margarida F. Jacome
CODES
2007
IEEE
14 years 4 months ago
Embedded software development on top of transaction-level models
Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write o...
Wolfgang Klingauf, Robert Günzel, Christian S...
CODES
2001
IEEE
14 years 2 months ago
RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors
The paper proposes a novel software-pipelining algorithm, Register Sensitive Force Directed Retiming Algorithm (RSFDRA), suitable for optimizing compilers targeting embedded VLIW ...
Cagdas Akturan, Margarida F. Jacome
ISSS
1996
IEEE
169views Hardware» more  ISSS 1996»
14 years 2 months ago
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
Alessandro Balboni, William Fornaciari, M. Vincenz...