Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
Because of the large number of possible combinations for the fuel assembly loading in the core, the design of the loading pattern (LP) is a complex optimization problem. It requir...
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
Testing embedded memories is becoming an industry-wide concern with the advent of deep-submicron technology and system-on-chip applications. We present a prototype chip for a progr...
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...