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146
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SEUS
2007
IEEE
15 years 10 months ago
A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture
In this paper we present a distributed Hardware-in-the-Loop (HiL) simulation approach that supports the verification and validation activities in an integrated architecture as rec...
Martin Schlager, Roman Obermaisser, Wilfried Elmen...
ICCD
2004
IEEE
172views Hardware» more  ICCD 2004»
16 years 17 days ago
A Signal Integrity Test Bed for PCB Buses
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
Jihong Ren, Mark R. Greenstreet
129
Voted
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
16 years 4 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
124
Voted
ATS
1998
IEEE
112views Hardware» more  ATS 1998»
15 years 8 months ago
Integrated Current Sensing Device for Micro IDDQ Test
A current sensing device, namely Hall Effect MOSFET (HEMOS) is proposed. It is experimentally shown that the HEMOS enables a non-contacting, and non-disturbing current measurement...
Koichi Nose, Takayasu Sakurai
171
Voted
ICDE
2005
IEEE
78views Database» more  ICDE 2005»
16 years 5 months ago
THALIA: Test Harness for the Assessment of Legacy Information Integration Approaches
Joachim Hammer, Michael Stonebraker, Oguzhan Topsa...