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» End-to-end validation of architectural power models
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DATE
2010
IEEE
202views Hardware» more  DATE 2010»
14 years 24 days ago
FlashPower: A detailed power model for NAND flash memory
Abstract— Flash memory is widely used in consumer electronics products, such as cell-phones and music players, and is increasingly displacing hard disk drives as the primary stor...
Vidyabhushan Mohan, Sudhanva Gurumurthi, Mircea R....
DAC
2012
ACM
11 years 10 months ago
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs
Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and pow...
Xin Zhao, Michael Scheuermann, Sung Kyu Lim
TWC
2008
129views more  TWC 2008»
13 years 7 months ago
Spatial Multiplexing Architectures with Jointly Designed Rate-Tailoring and Ordered BLAST Decoding - Part II: A Practical Method
The study of the class of new spatial multiplexing architectures (SMAs) is continued. As introduced in Part I of this paper, the SMAs consist of joint design of rate and power all...
Yi Jiang, Mahesh K. Varanasi
DAC
2010
ACM
13 years 8 months ago
Performance and power modeling in a multi-programmed multi-core environment
This paper describes a fast, automated technique for accurate on-line estimation of the performance and power consumption of interacting processes in a multi-programmed, multi-cor...
Xi Chen, Chi Xu, Robert P. Dick, Zhuoqing Morley M...
CAMP
2005
IEEE
13 years 9 months ago
Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor
Abstract— In this paper we address the problem of the architectural exploration from the energy/performance point of view of a VLIW processor for embedded systems. We also consid...
Domenico Barretta, Gianluca Palermo, Mariagiovanna...