Sciweavers

63 search results - page 4 / 13
» End-to-end validation of architectural power models
Sort
View
ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
14 years 4 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
DATE
2008
IEEE
149views Hardware» more  DATE 2008»
14 years 2 months ago
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks
Accurate power and performance figures are critical to assess the effective design of possible sensor node architectures in Body Area Networks (BANs) since they operate on limite...
Francisco J. Rincón, Michele Paselli, Joaqu...
PATMOS
2007
Springer
14 years 1 months ago
XEEMU: An Improved XScale Power Simulator
Energy efficiency is a top requirement in embedded system design. Understanding the complex issue of software power consumption in early design phases is of extreme importance to m...
Zoltán Herczeg, Ákos Kiss, Daniel Sc...
ICCAD
2003
IEEE
144views Hardware» more  ICCAD 2003»
14 years 4 months ago
A High-level Interconnect Power Model for Design Space Exploration
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
Pallav Gupta, Lin Zhong, Niraj K. Jha
PATMOS
2007
Springer
14 years 1 months ago
Optimization for Real-Time Systems with Non-convex Power Versus Speed Models
Abstract. Until now, the great majority of research in low-power systems has assumed a convex power model. However, recently, due to the confluence of emerging technological and ar...
Ani Nahapetian, Foad Dabiri, Miodrag Potkonjak, Ma...