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» Energy Efficient Scheduling for Datapath Synthesis
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VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
14 years 8 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan
ISCAS
2003
IEEE
103views Hardware» more  ISCAS 2003»
14 years 28 days ago
An ILP-based scheduling scheme for energy efficient high performance datapath synthesis
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
14 years 8 months ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan
ASPDAC
1995
ACM
77views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A scheduling algorithm for synthesis of bus-partitioned architectures
- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi T...
VLSID
2005
IEEE
157views VLSI» more  VLSID 2005»
14 years 8 months ago
Energy Efficient Hardware Synthesis of Polynomial Expressions
Polynomial expressions are used to approximate a wide variety of functions commonly found in signal processing and computer graphics applications. Computing these polynomial expre...
Anup Hosangadi, Farzan Fallah, Ryan Kastner