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» Energy benchmarks: a detailed analysis
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DATE
2009
IEEE
141views Hardware» more  DATE 2009»
14 years 5 months ago
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
– The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects...
Shashikanth Bobba, Jie Zhang, Antonio Pullini, Dav...
ACSAC
2008
IEEE
14 years 5 months ago
Defending Against Attacks on Main Memory Persistence
Main memory contains transient information for all resident applications. However, if memory chip contents survives power-off, e.g., via freezing DRAM chips, sensitive data such a...
William Enck, Kevin R. B. Butler, Thomas Richardso...
CODES
2006
IEEE
14 years 4 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
ASPLOS
2004
ACM
14 years 4 months ago
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...
BMCBI
2007
134views more  BMCBI 2007»
13 years 11 months ago
Efficient pairwise RNA structure prediction using probabilistic alignment constraints in Dynalign
Background: Joint alignment and secondary structure prediction of two RNA sequences can significantly improve the accuracy of the structural predictions. Methods addressing this p...
Arif Ozgun Harmanci, Gaurav Sharma, David H. Mathe...