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» Energy exploration and reduction of SDRAM memory systems
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CASES
2005
ACM
13 years 9 months ago
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
ICCD
2001
IEEE
84views Hardware» more  ICCD 2001»
14 years 4 months ago
Static Energy Reduction Techniques for Microprocessor Caches
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, S...
DATE
2002
IEEE
130views Hardware» more  DATE 2002»
14 years 12 days ago
Assigning Program and Data Objects to Scratchpad for Energy Reduction
The number of embedded systems is increasing and a remarkable percentage is designed as mobile applications. For the latter, the energy consumption is a limiting factor because of...
Stefan Steinke, Lars Wehmeyer, Bo-Sik Lee, Peter M...
TVLSI
2008
169views more  TVLSI 2008»
13 years 7 months ago
Energy-Aware Flash Memory Management in Virtual Memory System
The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage. Recently, flash memory becomes a popular storage alternative for ma...
Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng
ASPDAC
2008
ACM
97views Hardware» more  ASPDAC 2008»
13 years 9 months ago
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt