319 search results - page 23 / 64 » Energy minimization using multiple supply voltages |
142
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TVLSI
2002
15 years 3 months ago
2002
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
118
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ARITH
2007
IEEE
15 years 8 months ago
2007
IEEE
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determi...
136
Voted
ASAP
2005
IEEE
15 years 9 months ago
2005
IEEE
This paper explores low-power reliable microarchitectures for addition. Power, speed, and reliability (both defect- and fault-tolerance) are important metrics of system design, sp...
ISLPED
2003
ACM
15 years 9 months ago
2003
ACM
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
180
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RTSS
1998
IEEE
15 years 8 months ago
1998
IEEE
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...