122 search results - page 3 / 25 » Energy reduction in multiprocessor systems using transaction... |
ARC
2010
Springer
13 years 11 months ago
2010
Springer
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
MICRO
2008
IEEE
13 years 7 months ago
2008
IEEE
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
IPPS
2003
IEEE
14 years 25 days ago
2003
IEEE
Our recent work on uniprocessor and single-node multiprocessor (SMP) active memory systems uses address remapping techniques in conjunction with extended cache coherence protocols...
ISCA
1993
IEEE
13 years 11 months ago
1993
IEEE
A shared data structure is lock-free if its operations do not require mutual exclusion. If one process is interrupted in the middle of an operation, other processes will not be pr...
CC
2007
Springer
14 years 1 months ago
2007
Springer
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...