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ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
14 years 4 months ago
Two dimensional highly associative level-two cache design
High associativity is important for level-two cache designs [9]. Implementing CAM-based Highly Associative Caches (CAM-HAC), however, is both costly in hardware and exhibits poor s...
Chuanjun Zhang, Bing Xue
SENSYS
2010
ACM
13 years 5 months ago
Design and evaluation of a versatile and efficient receiver-initiated link layer for low-power wireless
We present A-MAC, a receiver-initiated link layer for low-power wireless networks that supports several services under a unified architecture, and does so more efficiently and sca...
Prabal Dutta, Stephen Dawson-Haggerty, Yin Chen, C...
SLIP
2006
ACM
14 years 1 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
ICRA
2007
IEEE
127views Robotics» more  ICRA 2007»
14 years 2 months ago
Design of an Autonomous Jumping Microrobot
– This paper presents the design and initial results for an autonomous jumping microrobot. At the millimeter size scale, jumping can offer numerous advantages for efficient locom...
Sarah Bergbreiter, Kristofer S. J. Pister
MICRO
2009
IEEE
137views Hardware» more  MICRO 2009»
14 years 2 months ago
ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem
Dynamic Random Access Memory (DRAM) is used as the bulk of the main memory in most computing systems and its energy and power consumption has become a first-class design considera...
Ciji Isen, Lizy Kurian John