29 search results - page 4 / 6 » Energy-recovery CMOS for highly pipelined DSP designs |
IPPS
2002
IEEE
14 years 1 months ago
2002
IEEE
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
ISCAS
2002
IEEE
14 years 1 months ago
2002
IEEE
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
NOCS
2009
IEEE
14 years 3 months ago
2009
IEEE
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
ASAP
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
Polar modulation techniques offer the capability of multimode wireless system and the potential for the high efficiency Power Amplifier (PA). This paper describes a new design of D...