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ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
14 years 6 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...
FPGA
1997
ACM
149views FPGA» more  FPGA 1997»
14 years 2 months ago
Signal Processing at 250 MHz Using High-Performance FPGA's
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
Brian Von Herzen
CSREAESA
2004
13 years 11 months ago
Driving Fully-Adiabatic Logic Circuits Using Custom High-Q MEMS Resonators
To perform digital logic in CMOS in a truly adiabatic (asymptotically thermodynamically reversible) fashion requires that logic transitions be driven by a quasitrapezoidal (flat-t...
Venkiteswaran Anantharam, Maojiao He, Krishna Nata...
ICCD
1995
IEEE
85views Hardware» more  ICCD 1995»
14 years 1 months ago
A high-performance asynchronous SCSI controller
We describe thedesign of a high performance asynchronous SCSI Small Computer Systems Interface controller data path and the associated control circuits. The data path is an asyn...
Kenneth Y. Yun, David L. Dill
CASES
2008
ACM
13 years 12 months ago
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...