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CODES
2003
IEEE
14 years 23 days ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
DATE
2003
IEEE
124views Hardware» more  DATE 2003»
14 years 23 days ago
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
Wonjoon Choi, Kia Bazargan
GLVLSI
2003
IEEE
171views VLSI» more  GLVLSI 2003»
14 years 23 days ago
Combining wire swapping and spacing for low-power deep-submicron buses
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
Enrico Macii, Massimo Poncino, Sabino Salerno
JSA
2006
113views more  JSA 2006»
13 years 7 months ago
A power-efficient TCAM architecture for network forwarding tables
Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable m...
Taskin Koçak, Faysal Basci
PODC
2009
ACM
14 years 2 months ago
Fast scalable deterministic consensus for crash failures
We study communication complexity of consensus in synchronous message-passing systems with processes prone to crashes. The goal in the consensus problem is to have all the nonfaul...
Bogdan S. Chlebus, Dariusz R. Kowalski, Michal Str...