67 search results - page 4 / 14 » Enhanced Code Compression for Embedded RISC Processors |
FCCM
2009
IEEE
14 years 1 months ago
2009
IEEE
The Ambric Massively Parallel Processor Array (MPPA) is a device that contains 336 32-bit RISC processors and is appropriate for embedded systems due to its relatively small physi...
CODES
2008
IEEE
13 years 6 months ago
2008
IEEE
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
DATE
2006
IEEE
14 years 19 days ago
2006
IEEE
Today’s nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability fail...
SBCCI
2005
ACM
14 years 4 days ago
2005
ACM
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
DAC
2003
ACM
14 years 7 months ago
2003
ACM
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that co...