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» Enhanced Code Compression for Embedded RISC Processors
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TVLSI
2002
98views more  TVLSI 2002»
13 years 7 months ago
Minimizing memory access energy in embedded systems by selective instruction compression
We propose a technique for reducing the energy spent in the memory-processor interface of an embedded system during the execution of firmware code. The method is based on the idea ...
Luca Benini, Alberto Macii, Enrico Macii, Massimo ...
ASPDAC
2004
ACM
132views Hardware» more  ASPDAC 2004»
14 years 29 days ago
A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications
– A low-power graphics LSI is designed and implemented for mobile multimedia applications. The LSI contains a 32bit RISC processor with enhanced MAC, a 3D rendering engine, progr...
Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun S...
SBACPAD
2004
IEEE
86views Hardware» more  SBACPAD 2004»
13 years 9 months ago
Multi-Profile Instruction Based Compression
Code compression has been used to minimize the memory area requirement of embedded systems. Recently, performance improvement and energy consumption reductionare observed as a by-...
Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Ce...
ISLPED
1999
ACM
100views Hardware» more  ISLPED 1999»
13 years 12 months ago
Selective instruction compression for memory energy reduction in embedded systems
We propose a technique for reducing the energy required by rmware code to execute on embedded systems. The method is based on the idea of compressing the most commonly executed in...
Luca Benini, Alberto Macii, Enrico Macii, Massimo ...
CHES
2007
Springer
327views Cryptology» more  CHES 2007»
14 years 1 months ago
On the Power of Bitslice Implementation on Intel Core2 Processor
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
Mitsuru Matsui, Junko Nakajima