Sciweavers

146 search results - page 4 / 30
» Enhanced clustered voltage scaling for low power
Sort
View
ISCAPDCS
2008
13 years 9 months ago
Parallel Embedded Systems: Where Real-Time and Low-Power Meet
This paper introduces a combination of models and proofs for optimal power management via Dynamic Frequency Scaling and Dynamic Voltage Scaling. The approach is suitable for syste...
Zdravko Karakehayov, Yu Guo
FPL
2004
Springer
98views Hardware» more  FPL 2004»
14 years 25 days ago
Power-Driven Design Partitioning
In order to enable efficient integration of FPGAs into cost effective and reliable high-performance systems as well potentially into low power mobile systems, their power efficienc...
Rajarshi Mukherjee, Seda Ogrenci Memik
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
14 years 1 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ISCAS
2007
IEEE
135views Hardware» more  ISCAS 2007»
14 years 1 months ago
Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology
Abstract—In the nanometer-scale CMOS technology, the gateoxide thickness has been scaled down to support a higher operating speed under a lower power supply (1xVDD). However, the...
Ming-Dou Ker, Hung-Tai Liao
HIPEAC
2007
Springer
14 years 1 months ago
Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems
Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches,...
Major Bhadauria, Sally A. McKee, Karan Singh, Gary...