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MICRO
1996
IEEE
96views Hardware» more  MICRO 1996»
13 years 11 months ago
Exceeding the Dataflow Limit via Value Prediction
For decades, the serialization constraints imposed by true data dependences have been regarded as an absolute limit--the dataflow limit--on the parallel execution of serial progra...
Mikko H. Lipasti, John Paul Shen
CASES
2003
ACM
13 years 11 months ago
Efficient spill code for SDRAM
Processors such as StrongARM and memory such as SDRAM enable efficient execution of multiple loads and stores in a single instruction. This is particularly useful in connection wi...
V. Krishna Nandivada, Jens Palsberg
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
14 years 2 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li
ICCS
2003
Springer
14 years 25 days ago
Terascale I/O Solutions
PSC has architected and delivered the TCS-1 machine, a Terascale Computing System for use in unclassified research. PSC has enhanced the effective usability and utilization of this...
Nathan Stone, John Kochmar, Paul Nowoczynski, J. R...
HPCA
2009
IEEE
14 years 8 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth