1534 search results - page 6 / 307 » Error Reporting Logic |
DFT
2003
IEEE
14 years 21 days ago
2003
IEEE
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...
KR
2000
Springer
13 years 11 months ago
2000
Springer
We explore the possibility of a logic where a conclusion substantially improves over its premise(s): Specifically, we intend to rule out inference steps such that the premise conv...
FASE
2009
Springer
14 years 2 months ago
2009
Springer
Abstract. Software is often tested with unit tests, in which each procedure is executed in isolation, and its result compared with an expected value. Individual tests correspond to...
CP
1998
Springer
13 years 11 months ago
1998
Springer
Abstract. We propose a general framework for assertion-based debugging of constraint logic programs. Assertions are linguistic constructions which allow expressing properties of pr...