122 search results - page 5 / 25 » Error tolerant associative memory |
DFT
2009
IEEE
14 years 2 months ago
2009
IEEE
Hybrid CMOS/non-CMOS memories, in short hybrid memories, have been lauded as future ultra-capacity data memories. Nonetheless, such memories are going to suffer from high degree o...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Dual-execution/checkpointing based transient error tolerance techniques have been widely used in the high-end mission critical systems. These techniques, however, are not very att...
PRDC
2006
IEEE
14 years 1 months ago
2006
IEEE
As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
- The problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theory-based approach. This paper provides a theoretical fra...
SIGADA
1998
Springer
13 years 12 months ago
1998
Springer
Our institute has been developing the only publicly available implementation of the Ada 95 Distributed Systems Annex for several years in strong collaboration with Ada Core Techno...