122 search results - page 7 / 25 » Error tolerant associative memory |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
RTCSA
2008
IEEE
14 years 2 months ago
2008
IEEE
Real-time systems typically have to satisfy complex requirements, mapped to the task attributes, eventually guaranteed by the underlying scheduler. These systems consist of a mix ...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Languages such as C and C++ use unsafe manual memory management, allowing simple bugs (i.e., accesses to an object after deallocation) to become the root cause of exploitable secu...
ICDM
2003
IEEE
14 years 28 days ago
2003
IEEE
Abstract. We present a new distributed association rule mining (D-ARM) algorithm that demonstrates superlinear speed-up with the number of computing nodes. The algorithm is the fi...
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...