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» Estimating design time for system circuits
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CODES
2007
IEEE
14 years 2 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
SAC
2004
ACM
14 years 1 months ago
Forest trees for on-line data
This paper presents an hybrid adaptive system for induction of forest of trees from data streams. The Ultra Fast Forest Tree system (UFFT) is an incremental algorithm, with consta...
João Gama, Pedro Medas, Ricardo Rocha
TVLSI
2010
13 years 3 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
COMCOM
2006
112views more  COMCOM 2006»
13 years 8 months ago
Dynamic server selection using fuzzy inference in content distribution networks
To accommodate the exponential growth of Web traffic, Content Distribution Networks (CDN) have been designed and deployed to distribute content to different cache servers, and to ...
Lin Cai, Jun Ye, Jianping Pan, Xuemin Shen, Jon W....
ACSD
2010
IEEE
255views Hardware» more  ACSD 2010»
13 years 6 months ago
From POOSL to UPPAAL: Transformation and Quantitative Analysis
POOSL (Parallel Object-Oriented Specification Language) is a powerful general purpose system-level modeling language. In research on design space exploration of motion control syst...
Jiansheng Xing, Bart D. Theelen, Rom Langerak, Jac...