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» Estimating design time for system circuits
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ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Sleep transistor sizing using timing criticality and temporal currents
— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to...
Anand Ramalingam, Bin Zhang, Anirudh Devgan, David...
GLOBECOM
2006
IEEE
14 years 1 months ago
Alamouti Space-Time Coded OFDM Systems in Time- and Frequency-Selective Channels
Abstract— We propose low-complexity equalizers for Alamouti space-time coded orthogonal frequency-division multiplexing (OFDM) systems in time- and frequency-selective channels, ...
Kun Fang, Geert Leus, Luca Rugini
VTS
2008
IEEE
104views Hardware» more  VTS 2008»
14 years 1 months ago
Signature Rollback - A Technique for Testing Robust Circuits
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
Uranmandakh Amgalan, Christian Hachmann, Sybille H...
DAC
2009
ACM
14 years 8 months ago
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies ...
Jürgen Teich, Martin Lukasiewycz, Michael Gla...
ASPDAC
2006
ACM
121views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Efficient early stage resonance estimation techniques for C4 package
- In this paper, we study the relationship between C4 package resonance effects and logical switching timing correlations, which has not been thoroughly investigated in the past. W...
Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hon...