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» Estimating design time for system circuits
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TCOM
2010
106views more  TCOM 2010»
13 years 5 months ago
On the system level prediction of joint time frequency spreading systems with carrier phase noise
- Phase noise is a topic of theoretical and practical interest in electronic circuits. Although progress has been made in the characterization of its description, there are still c...
Youssef Nasser, Mathieu Des Noes, Laurent Ros, Gen...
ISQED
2007
IEEE
104views Hardware» more  ISQED 2007»
14 years 1 months ago
System Level Estimation of Interconnect Length in the Presence of IP Blocks
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...
Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh
ISQED
2006
IEEE
155views Hardware» more  ISQED 2006»
14 years 1 months ago
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
Bin Zhang, Wei-Shen Wang, Michael Orshansky
IPPS
2002
IEEE
14 years 9 days ago
Overview of Hydra: A Concurrent Language for Synchronous Digital Circuit Design
Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit speci...
John O'Donnell
DAC
1999
ACM
13 years 11 months ago
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...
Alex Doboli, Adrián Núñez-Ald...